Application of the Latency Insertion Method (LIM) to the Modeling of CDM ESD Event

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-lm CMOS technology to achieve 1-kV CDM ESD robustness. 2007 Elsevier Ltd. All rights reserved.

Turn-on Speed of Grounded Gate Nmos Esd Protection Transistors

The turn-on speed of nMOS transistors (nMOST) is of paramount importance for robust Charged Device Model (CDM) protection circuitry. In this paper the nMOST turn-on time has been measured for the first time in the sub-halve nanosecond range with a commercial e-beam tester. The method may be used to improve CDM-ESD hardness by investigating the CDM pulse responses within circuit. Furthermore it ...

Multivariate Frailty Modeling in Joint Analyzing of Recurrent Events with Terminal Event and its Application in Medical Data

Background and Objectives: In many medical situations, people can experience recurrent events with a terminal event. If the terminal event is considered a censor in this type of data, the assumption of independence in the analysis of survival data may be violated. This study was conducted to investigate joint modeling of frequent events and a final event (death) in breast cancer patients using ...

Application of ESD and PR+Wong Sandler Mixing Rule Equations of State to Study Methane Hydrate Formation in the Presence of Different Inhibitors

Investigation on CDM ESD events at core circuits in a 65-nm CMOS process

Among three chip-level electrostatic discharge (ESD) test standards, which were human-body model (HBM), machine model (MM), and charged-device model (CDM), the CDM ESD events became critical due to the larger and faster discharging currents. Besides input/output (I/O) circuits which were connected to I/O pads, core circuits also suffered from CDM ESD events caused by coupled currents between I/...